1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a capacitor element and a method of manufacturing the device.
2. Description of the Related Art
An MIS structure composed of an upper metal electrode, a dielectric and a lower silicon electrode is currently adopted for a capacitor element of a dynamic random access memory (DRAM) merchandised as a product. To secure the performance of DRAM, the capacitance of the capacitor element is required to maintain a constant value. However, because the size of a memory cell is reduced due to the high integration each time the product generation alternates, the area and volume allowed for layout of the capacitor element are reduced, and it becomes difficult to secure the capacitance of the capacitor element.
A capacitor element of DRAM has a lower electrode denoting an accumulation electrode, an upper electrode denoting a plate electrode and a dielectric insulating film placed between the lower electrode and the upper electrode. As is well known, when the thickness of the dielectric insulating film is decided, the capacitance of the capacitor element is decided according to areas of the lower electrode and the upper electrode and the dielectric constant of the dielectric insulating film. As a technique for securing the areas of the lower electrode and the upper electrode, a method of enlarging an effective area by forming uneven portions on a surface of an electrode has been already used. Further, as a technique for improving the dielectric constant of the capacitor element, the configuration using a material of a high dielectric constant such as tantalum oxide or the like has been already used. However, even though these methods of securing the capacitance were adopted, because further integration is required for DRAM in recent years, it is becoming difficult to secure a space for forming uneven portions on the surface of the lower electrode. Further, in the MIS structure obtained by using silicon for the lower electrode and using tantalum oxide for the dielectric insulating film, a problem arises that silicon oxide having a low dielectric constant is inevitably formed on a boundary face between the silicon and tantalum oxide. Therefore, the improvement of the dielectric constant is gradually reaching a limit.
To solve the above-described problems, an MIM structure using metal as a material of the lower electrode has been examined. The MIM structure is composed of an upper metal electrode, a dielectric and a lower metal electrode. In case of the MIM structure, the problem of limiting the dielectric constant in the MIS structure can be avoided.
However, when the MIM structure is adopted, a new problem arises in that a leak current increases. Many metals such as titanium nitride, tungsten and the like already used for the semiconductor integrated circuit device are considerably easily oxidized. Therefore, in the structure using an easily-oxidized metal for the lower electrode as it is, tantalum oxide film is formed on the lower electrode, and heat treatment is performed for the tantalum oxide film in the oxygen atmosphere to introduce oxygen into oxygen defects of the tantalum oxide film. However, because oxygen is consumed in the lower electrode made of metal, a capacitor element is formed while the oxygen defects remain in the tantalum oxide film regardless of the heat treatment.
When oxygen defects exist in the dielectric insulating film of the capacitor element, even though attempts to accumulate a charge in the capacitor element, a leak current between the electrodes through the oxygen defects is increased. Therefore, the capacitor element becomes defective.
To avoid this problem, it is effective to use a conducting material such as platinum, ruthenium, iridium or the like, which is comparatively difficult to oxidize, for the lower electrode. Further, to manufacture a capacitor element having a three-dimensional structure, in view of securing step coverage, it is required to satisfy a necessary condition that the capacitor element can be formed according to a chemical vapor deposition (CVD) method and another necessary condition that the capacitor element can be processed. To satisfy these conditions, ruthenium is the most preferable as a material.
The configuration of DRAM will be now described.
FIG. 1 is a sectional view showing an example of the configuration of DRAM.
DRAM shown in FIG. 1 has a memory array region and a peripheral circuit region. Memory cells are formed in the memory array region, and circuits for writing and reading out information in/from the memory cells are formed in the peripheral circuit region.
As shown in FIG. 1, in the memory array region, first p-well layer 103 (p-type impurity diffusion layer) is formed in p-type silicon substrate 101 (semiconductor substrate) ranging from a surface thereof to a position of a predetermined depth, and n-well layer 102 (n-type impurity diffusion layer) is formed so as to surround a side surface and a bottom surface of first p-well layer 103. In the peripheral circuit region, second p-well layer 104 (p-type impurity diffusion layer) is formed in p-type silicon substrate 101 (semiconductor substrate) ranging from the surface thereof to a position of another predetermined depth. N-well layer 102 and second p-well layer 104 are insulated and separated from each other by element separation region 105.
Next, the configuration of transistors of a memory cell will be described.
In FIG. 1, transistors 106 and 107 are formed in first p-well layer 103. Transistor 106 has both drain electrode 108 and source electrode 109a formed in first p-well layer 103 and gate electrode 111a formed on first p-well layer 103 through gate insulating film 110. Transistor 107 has drain electrode 112a, gate electrode 111b formed on gate insulating film 110 and source electrode 109a common with transistor 106. Transistors of a memory cell such as transistors 106 and 107 and the like are covered with first interlayer insulating film 113.
Each of transistors 106 and 107 is used as a switching element for selecting a capacitor element, gate electrodes 111a and 111b are used as word lines, and a bit line is connected to source electrode 109a. 
Each transistor of the memory cell described above is an n-type metal oxide semiconductor (MOS) in which each of a drain electrode and a source electrode is composed of an n-type impurity diffusion layer. Because transistor 106 has the same configuration as that of transistor 107, the configuration of the memory array region will be described in detail below by using transistor 107 and a capacitor element connected with transistor 107 as an example.
The configuration of a bit line connected with a transistor will be initially described.
A bit line is connected with source electrode 109a through both polycrystalline silicon 115 packed in contact hole 114 formed in first interlayer insulating film 113 and a bit line contact placed on polycrystalline silicon 115. The bit line is configured by stacking up tungsten nitride 119 and tungsten 120 in that order. The bit line contact is configured by stacking up titanium silicide 116, titanium nitride 117 and tungsten 118. A side surface and an upper surface of the bit line are covered with second interlayer insulating film 121.
Next, the configuration of a capacitor element of the memory cell will be described.
A capacitor element has lower electrode 124a, upper electrode 126 and insulating film 125 placed between lower electrode 124a and upper electrode 126. Lower electrode 124a is formed in a shape and has a circular bottom and a cylindrical side wall (hereinafter, called crown structure), and the side wall and the bottom of an opening of lower electrode 124a are covered with dielectric insulating film 125. Upper electrode 126 is formed so as to cover the entire memory array region, and fourth interlayer insulating film 127 is formed on upper electrode 126.
Lower electrode 124a is connected with drain electrode 112a of transistor 107 through silicon plug 122 penetrating through both first interlayer insulating film 113 and second interlayer insulating film 121. Silicon plug 122 is configured by packing silicon in a contact hole placed at predetermined positions of first interlayer insulating film 113 and second interlayer insulating film 121. A capacitor element having lower electrode 124b, dielectric insulating film 125 and upper electrode 126 is connected with drain electrode 108 of transistor 106.
Next, the configuration of transistor 150 and wiring formed in the peripheral circuit region will be described.
Transistor 150 has both source electrode 109b and drain electrode 112b formed in second p-well layer 104 and gate electrode 111c formed on gate insulating film 110.
Drain electrode 112b is connected with a first wiring layer through metal buried in contact hole 128 formed at a predetermined position of first interlayer insulating film 113. In contact hole 128, titanium silicide 116, titanium nitride 117 and tungsten 118 are packed in that order.
The first wiring layer has tungsten nitride 119 and tungsten 120. The first wiring layer is connected with a second wiring layer through tungsten nitride 130 and tungsten 131 packed in contact hole 129 penetrating through second interlayer insulating film 121, third interlayer insulating film 123 and fourth interlayer insulating film 127. The second wiring layer connected with the first wiring layer has titanium nitride 132, aluminum 133 and titanium nitride 134.
In upper electrode 126 provided in the memory array region, leader wiring 135, of which a portion reaches the peripheral circuit region, is arranged. Leader wiring 135 is connected with the second wiring layer through both titanium nitride 136 and tungsten 137 packed in a contact hole arranged in a predetermined position of fourth interlayer insulating film 127. The second wiring layer connected with leader wiring 135 has titanium nitride 138, aluminum 139 and titanium nitride 140. Gate electrode wiring 111d acting as a wiring is formed on element separation region 105 insulating and separating n-well layer 102 from second p-well layer 104.
Here, transistor 150 is formed of an n-type MOS. However, in the peripheral circuit region, a p-type MOS transistor (not shown), in which each of a drain electrode and a source electrode is composed of a p-type impurity diffusion layer, is also arranged in an n-well layer (not shown) composed of an n-type impurity diffusion layer.
In the memory array region and the peripheral circuit region, a interlayer insulating film, a contact and a wiring layer not shown are, if necessary, formed on the second wiring layer. As described above, DRAM is formed (for example, refer to Published Unexamined Japanese Patent Application No. 2001-94071).
Next, a method of manufacturing capacitor elements of DRAM shown in FIG. 1 will be described. Each capacitor element described below is configured by using ruthenium for a lower electrode.
FIGS. 2A to 2G are sectional views showing a process of manufacturing conventional capacitor elements. The detailed description of the process of forming the transistor is omitted. Further, openings of a contact hole and the like and patterns of a wiring and the like are formed, in case of no specific description, by using a known lithography process and a known etching process.
As shown in FIG. 2A, first interlayer insulating film 203 is formed so as to cover word lines 202 composed of a conductive film formed on silicon substrate 201.
Thereafter, contact holes are formed in first interlayer insulating film 203, and first silicon plugs 204 are formed by packing silicon into the contact holes. Word lines 202 are gate electrodes of transistors formed on a gate insulating film not shown, and the contact holes are arranged at positions at which a source electrode and drain electrodes not shown are formed in silicon substrate 201.
Then, after second interlayer insulating film 205 is deposited on first interlayer insulating film 203, an opening is formed in second interlayer insulating film 205 so as to expose an upper surface of one first silicon plug 204 connected with the source electrode, and bit line contact 206 is formed by packing a conductive film into the opening. Thereafter, a bit line 207 connected with bit line contact 206 is formed.
Thereafter, third interlayer insulating film 208 composed of silicon oxide and fourth interlayer insulating film 209 composed of silicon nitride are deposited in that order on second interlayer insulating film 205. Thereafter, openings penetrating through second interlayer insulating film 205, third interlayer insulating film 208 and fourth interlayer insulating film 209 are formed so as to expose upper surfaces of the other first silicon plugs 204 connected with drain electrodes, and second silicon plugs 210 are formed by packing silicon into the openings.
Thereafter, as shown in FIG. 2B, upper portions of second silicon plugs 210 are removed by etching, and recesses 211 are formed so as to place upper surfaces of second silicon plugs 210 at a position corresponding to almost half of a film thickness of fourth interlayer insulating film 209.
Then, after titanium nitride is formed on the entire surface of fourth interlayer insulating film 209 so as to sufficiently bury the recesses 211, the titanium nitride placed on no recess is removed. Thereafter, barrier metal 212 is buried into each of recesses 211 (FIG. 2C). Barrier metals 212 are arranged to prevent the reaction between silicon of second silicon plugs 210 and a film of ruthenium formed later. It is preferable that these barrier metals 212 are formed according to a CVD method having excellent step coverage.
Then, after fifth interlayer insulating film 213 composed of silicon nitride and sixth interlayer insulating film 214 composed of silicon oxide having a film thickness of almost 1.5 μm are deposited on the fourth interlayer insulating film 209, portions of fifth interlayer insulating film 213 and sixth interlayer insulating film 214 are removed at predetermined positions by etching until upper surfaces of barrier metals 212 are exposed, and cylinders 215 shaped in a cylindrical hole are formed (refer to FIG. 2D).
Thereafter, as shown in FIG. 2E, ruthenium having a film thickness of almost 5 nm is deposited on the entire surface by using a sputtering method, and a film of ruthenium 216 having a film thickness of almost 30 nm is formed according to the CVD method. Ruthenium formed according to the sputtering method acts as seed crystal (seed layer) of ruthenium formed according to the CVD method. Hereinafter, ruthenium formed according to the sputtering method is called sputtered ruthenium, and ruthenium formed according to the CVD method is called CVD ruthenium.
A film of the CVD ruthenium is formed by arbitrarily diluting ethylcyclopentadienylruthenium (Ru[C2H5C5H4]2: hereinafter, abbreviated to Ru(EtCp)2) with solvent such as tetrahydrofuran (THF) or the like (solvent other than THF is allowed) and reacting obtained vaporized gas with oxygen at a temperature of almost 300° C. After forming a film of the CVD ruthenium, the entire surface is coated with photoresist, is exposed to light and is developed so as to make photoresist 217 remain only in cylinders 215.
Thereafter, exposed ruthenium not covered with photoresist 217 is removed by an anisotropic dry etching using oxygen gas plasma. Further, photoresist 217 is removed by using solution having organic acid such as phenolalkylbenzenesulfonic acid as a main component, and cylinders 215, of which inner walls are covered with ruthenium 216, are formed (FIG. 2F).
Thereafter, as shown in FIG. 2G, sixth interlayer insulating film 214 supporting side walls composed of ruthenium 216 is removed, and lower electrodes of crown structures are formed. To remove sixth interlayer insulating film 214, a wet etching using solution having hydrofluoric acid as a main component is performed. Because fifth interlayer insulating film 213 placed under sixth interlayer insulating film 214 is composed of silicon nitride little etched by hydrofluoric acid, the etching performed for sixth interlayer insulating film 214 by using hydrofluoric acid is stopped by fifth interlayer insulating film 213.
In the manufacturing method described above, as shown in FIG. 2G, when sixth interlayer insulating film 214 is removed by the wet etching, because the support for the lower electrodes composed of ruthenium 216 is lost, a breakage 218 occurs. Or, a problem arises that at least one lower electrode collapses. Due to this problem, a capacitor element impossible to sufficiently accumulate charge is formed, and yield of DRAM is considerably lowered. Particularly, this problem frequently occurs when vibration is added during the wet etching process. Further, the breakage 218 or the collapse sometimes occurs due to heat treatment performed in a process of forming an insulating film after or the like the wet etching.
To examine causes of the above described problem, a film structure of ruthenium was observed, and an observed result will be described.
FIGS. 3A and 3B are modeling views showing a result of a cross section of a ruthenium film observed by using a transmission electron microscope. Particularly, FIG. 3A is a view showing a condition obtained just after forming ruthenium according to the CVD method, and FIG. 3B is a view showing a condition obtained after performing heat treatment for an observed sample.
The observed sample is obtained by forming silicon oxide 302 on a surface of silicon substrate 301, depositing ruthenium acting as seed crystal at a thickness of 5 nm according to the sputtering method and forming a film of ruthenium 303 at a film thickness of 30 nm according to the CVD method.
Even though ruthenium 303 is observed as a flat film by using a scanning electron microscope of almost two hundred thousand magnification, when ruthenium 303 is observed by using a transmission electron microscope of almost four million magnifications, as shown in FIG. 3A, it is realized that ruthenium 303 grows in a pole-like shape and do not form into a continuous film. Further, each of poles of ruthenium 303 is not vertical, but most of them are inclined. Therefore, adjacent poles come in contact with each other at head top portions of the poles, and spaces exist around each pole.
As shown in FIG. 3B, when heat treatment is performed for ruthenium 303 shown in FIG. 3A, poles are moved due to the heat treatment, the spaces are taken into the film of ruthenium 303, and the spaces remain in ruthenium 303 as voids 305.
Further, the film thickness of ruthenium 303 does not become uniform even after the heat treatment, a large number of thinned portions exist in the film, and deficiencies 306 having no ruthenium are generated. Because voids 305 and the thinned portions in the film lower the mechanical strength of the film, voids 305 and the thinned portions cause the lower electrodes to break or collapse.